# Altera Agilex 2X FPGAs add PCIe 7.0, 256Gbps transceivers, and QuartusIQ AI tooling

> **Key takeaway:** Altera's new Agilex 2X FPGA portfolio introduces PCIe 7.0 and 256Gbps SerDes connectivity alongside QuartusIQ, an AI-assisted development tool that reduced reference design effort from 32 to 3 hours in Altera's evaluation.

**Published:** 2026-11-01T17:53:06+00:00 
**Source:** LinuxGizmos 
**Category:** open-hardware 
**Canonical URL:** https://fosswire.org/news/altera-agilex-2x-fpgas-add-pcie-70-256gbps-transceivers-and-.html 

## Summary
Altera has unveiled Agilex 2X, its next-generation FPGA and SoC portfolio spanning four device families from cost-optimized edge parts to high-performance compute devices. The first announced family, Agilex 27, targets AI infrastructure and networking with 256Gbps transceivers, hardened 800GbE/1.6TbE Ethernet, PCIe 7.0, DDR5/LPDDR5X/LPDDR6 memory interfaces, and UCIe chiplet connectivity. The architecture incorporates third-generation HyperFlex fabric with distributed registers for retiming, updated AI tensor DSP blocks, and a multi-terabit HyperFlow data network that operates without consuming programmable logic resources.

Alongside the silicon, Altera released QuartusIQ, an AI assistant integrated into Quartus Prime Pro 26.3 that uses the Model Context Protocol to connect AI models with project data including device targets, IP configurations, constraints, and timing reports. QuartusIQ supports natural-language interaction for project setup, RTL development, debugging, and timing closure, and can run with cloud-hosted or local models including NVIDIA Nemotron on DGX Station. Altera claims the tool reduced logical and physical design entry for a 4Kp60 HDR video reference design from 32 engineer-hours to approximately 3 hours.

## Agilex 27 architecture and QuartusIQ capabilities
- **Agilex 27 transceivers and interconnect:** Configurable SerDes reach 256Gbps with hardened IP for 800GbE and 1.6TbE Ethernet, PCIe 6.0 and 7.0 support, plus UCIe chiplet connectivity for multi-die designs.
- **HyperFlex and HyperFlow fabric:** Third-generation HyperFlex distributes registers throughout routing for retiming and pipelining; HyperFlow provides a dedicated multi-terabit-per-second data network that avoids consuming standard programmable logic resources.
- **AI tensor DSP and security blocks:** Updated AI tensor DSP blocks target compute and signal-processing workloads; Secure Device Manager provides hardware root of trust, secure boot, post-quantum cryptography, MACsec, PCIe IDE, and inline memory encryption.
- **QuartusIQ MCP integration:** The AI assistant uses the Model Context Protocol to access Quartus project state including target devices, IP configurations, constraints, compilation reports, and timing data for natural-language-assisted development.
- **QuartusIQ deployment options:** Supports compatible cloud-hosted and locally deployed models, with specific on-premises support for NVIDIA DGX Station running Windows with NVIDIA Nemotron models.

## Why it matters
The PCIe 7.0 and 256Gbps SerDes in Agilex 27 push FPGA connectivity to match next-generation datacenter and AI infrastructure standards, giving Linux-based HPC and networking platforms early access to bandwidth that matches future CPU and GPU generations. For embedded Linux developers, the Arm-based hard processor and Nios V soft processor options across the four families provide flexible processing choices, though mainline Linux support status for the new Secure Device Manager and updated peripherals remains to be seen. QuartusIQ's Model Context Protocol approach could pressure other EDA vendors to open similar integration points, but its reliance on proprietary AI models and Windows-based DGX Station deployment raises questions about open-toolchain compatibility.