# AMD openSIL hits production on EPYC 9006 'Venice', all platforms boot without AGESA

> **Key takeaway:** AMD's open-source silicon initialization replacement for AGESA is now mandatory on all shipping Venice server platforms, with source code release promised within one quarter.

**Published:** 2026-11-13T18:20:29+00:00 
**Source:** Phoronix Benchmarks & Drivers 
**Category:** kernel-os 
**Canonical URL:** https://fosswire.org/news/amd-opensil-hits-production-on-epyc-9006-venice-all-platform.html 

## Summary
AMD's openSIL project has reached production status with the 6th Gen EPYC 9006 'Venice' processors, fulfilling the company's 2024 roadmap goal to replace proprietary AGESA firmware with open-source CPU silicon initialization. Unlike earlier Zen 5 proof-of-concept deployments that required Coreboot ports by third parties such as 3mdeb's Dasharo, Venice platforms ship with openSIL as the sole boot path—AMD confirmed that no Venice system has booted using the legacy AGESA codebase.

The open-source code for openSIL on Venice is scheduled for public release within one quarter of the product launch, maintaining the timeline AMD presented in earlier openSIL briefings. This development follows AMD's established pattern of adopting open firmware for server reference designs, which continue to use OpenBMC for baseboard management rather than proprietary alternatives.

## What openSIL production means for Venice firmware
- **Mandatory boot path:** Every shipping EPYC 9006 'Venice' platform on the SP7 socket boots exclusively through openSIL, with no AGESA fallback path available or used in any deployed system.
- **Source release timeline:** AMD committed to publishing the openSIL Venice source code within one quarter of the official product launch, matching the schedule outlined in prior openSIL presentations.
- **Proof-of-concept lineage:** Earlier openSIL support appeared as experimental Coreboot ports for Zen 5 on consumer MSI Ryzen and Gigabyte EPYC server motherboards via 3mdeb's Dasharo firmware distribution.
- **OpenBMC continuity:** AMD's reference motherboards for Venice continue the Genoa-era practice of using OpenBMC for baseboard management controller firmware instead of proprietary BMC implementations.
- **Coreboot enablement pathway:** Once openSIL Venice code is released, third-party firmware vendors and system integrators gain the foundation to port Coreboot to retail EPYC 9006 server motherboards independently of AMD direct involvement.

## Why it matters
The transition from optional proof-of-concept to mandatory production deployment of openSIL eliminates a major proprietary firmware dependency in AMD's server stack, giving Linux distributors and system administrators auditable, modifiable silicon initialization for the first time on a major x86 server platform. For open hardware advocates and security-focused deployments, this removes the AGESA binary blob that previously blocked fully open firmware stacks on EPYC systems, while the committed source release timeline provides concrete grounds for planning Coreboot and Libreboot enablement efforts.