My RISC-V Mentorship: The Problems Nobody Assigned Me
How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox Introduction One of the things I love most about RISC-V is that a student can read the same GitHub issues the experts read.
Executive Summary
How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox Introduction One of the things I love most about RISC-V is that a student can read the same GitHub issues the experts read. A few weeks into my mentorship, I was doing exactly that, browsing old issues out of curiosity. I found one from 2018. An engineer building one of the first compilers for the Vector extension had discovered that four of the new vector instructions collided head-on with JAL , the jump instruction.
Open Silicon & Gate-Level Hardware Inspection
From a silicon and hardware engineering viewpoint: - **Interface Neutrality:** Mitigates dependency on proprietary BSPs, empowering open toolchains to address hardware directly. - **Supply Chain Verification:** Schematics and open pinouts allow deterministic audits against silicon errata. - **Lifecycle Decoupling:** Decouples physical hardware utility from commercial vendor end-of-life obsolescence.
Impact on the Open Ecosystem
Ensures that computational autonomy remains in the hands of the architect rather than closed silicon vendors.