# My RISC-V Mentorship: The Problems Nobody Assigned Me

> **Key Architectural Takeaway:** How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox Introduction One of the things I love most about RISC-V is that a student can read the same GitHub issues the experts read.

**Published:** 2026-10-13T18:43:55+00:00 
**Source:** RISC-V International 
**Category:** open-hardware 
**Canonical URL:** https://fosswire.org/news/my-risc-v-mentorship-the-problems-nobody-assigned-me.html 

## Executive Summary
How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox Introduction One of the things I love most about RISC-V is that a student can read the same GitHub issues the experts read. A few weeks into my mentorship, I was doing exactly that, browsing old issues out of curiosity. I found one from 2018. An engineer building one of the first compilers for the Vector extension had discovered that four of the new vector instructions collided head-on with JAL , the jump instruction.

## Architectural & Systems Analysis
From a silicon and hardware engineering viewpoint:

- **Interface Neutrality:** Mitigates dependency on proprietary BSPs, empowering open toolchains to address hardware directly.
- **Supply Chain Verification:** Schematics and open pinouts allow deterministic audits against silicon errata.
- **Lifecycle Decoupling:** Decouples physical hardware utility from commercial vendor end-of-life obsolescence.

## Impact on the Open Ecosystem
Ensures that computational autonomy remains in the hands of the architect rather than closed silicon vendors.