SpacemiT V100: 46-core RISC-V server CPU claims first full RISC-V Server Spec compliance

SpacemiT has introduced the V100, a server-class RISC-V processor with 46 cores in a hybrid architecture combining six XiangShan Kunminghu V2R2 cores and 40 SpacemiT X100 cores. The chip supports up to 92 cores in dual-socket configurations, DDR5-4800 memory, and PCIe 5.0. The company claims it is the first processor to fully comply with the RISC-V Server Specification, with a firmware stack incorporating UEFI, ACPI, SMBIOS, OpenSBI, and SBI v3.0. Supported Linux distributions include Ubuntu, Debian, Fedora, Red Hat, Rocky Linux, openEuler, openKylin, and openRuyi.

V100 architecture and server platforms

• Hybrid core design: 6x XiangShan Kunminghu V2R2 (13-stage, six-issue OoO, 2.1GHz, 1MB private L2) + 40x SpacemiT X100 (12-stage, four-issue OoO, 2.4GHz, 2MB shared L2)
• Memory: 8-channel DDR5-4800, 307GB/s bandwidth, up to 2TB per socket (4TB dual-socket), with RDIMM and sideband ECC support
• I/O: 52 PCIe 5.0 lanes; 64MB system-level cache
• Process/TDP: 12nm, 120W
• ISA features: RVA23 profile, 256-bit RISC-V vector, vector cryptography, RISC-V hypervisor extension, PMP/ePMP
• Firmware compliance: UEFI, ACPI, SMBIOS, OpenSBI, SBI v3.0; passes UEFI Self Certification Test (BRS-I)
• Virtualization: KVM via upstream Linux kernel with H extension, AIA, and IOMMU
• Server variants: C2201 (2U compute, 12 U.2 NVMe bays), G5201 (4U AI, 8x FHFL accelerators, 400Gbps RDMA), S5236 (storage, up to 64 drive bays)

Why it matters

If the compliance claims hold, the V100 could reduce fragmentation in the RISC-V server ecosystem by providing a standardized platform that mainstream Linux distributions can target without vendor-specific patches. This addresses a longstanding barrier to RISC-V adoption in data centers.