Yosys Open Synthesis Suite: Yosys 0.69
Yosys 0.69 Commands and options Removed sum of products related parameters from "abc" pass.
Executive Summary
Yosys 0.69 Commands and options Removed sum of products related parameters from "abc" pass. Removed coolrunner2 and greenpak4 synthesis and related passes. Removed "nlutmap" pass. Removed "-retime", "-noabc9", "-abc2" and "-abc" options from synthesis passes. Removed "-[no]stderr" from "logger" pass. Various verific: Added "-sv2023" flag option to support System Verilog 2023.
Open Silicon & Gate-Level Hardware Inspection
From a silicon and hardware engineering viewpoint: - **Interface Neutrality:** Mitigates dependency on proprietary BSPs, empowering open toolchains to address hardware directly. - **Supply Chain Verification:** Schematics and open pinouts allow deterministic audits against silicon errata. - **Lifecycle Decoupling:** Decouples physical hardware utility from commercial vendor end-of-life obsolescence.
Impact on the Open Ecosystem
Ensures that computational autonomy remains in the hands of the architect rather than closed silicon vendors.