Altera Agilex 27 FPGA family adds Arm Cortex-A720/A520, PCIe 7.0, 256 Gbps SerDes

Altera has unveiled the Agilex 27 FPGA and SoC family, comprising 14 device models available in either FPGA-only or FPGA-plus-Arm-processor configurations. The new line targets AI infrastructure, high-speed networking, 6G and satellite communications, and aerospace and defense applications, with engineering samples expected in the second half of 2027.

The family scales from 866K to 17.6 million logic elements using a third-generation HyperFlex architecture, and integrates dual Cortex-A720 and dual Cortex-A520 cores in SoC variants running up to 2.3 GHz. Key I/O advancements include PCIe 7.0 x8 support, up to 32 GT SerDes transceivers at 256 Gbps, 1.6TbE Ethernet with hardened MACsec, and LPDDR6 memory support. A new HyperFlow data network enables direct data movement between fabric, memory, processors, and PCIe without consuming FPGA logic resources.

Architecture and I/O capabilities

• Arm processor subsystem: SoC variants include an Armv9.2 Hard Processor System with dual Cortex-A720 and dual Cortex-A520 cores at up to 2.3 GHz, 2MB shared L3 cache, 512KB on-chip ECC RAM, plus three TSN Ethernet MACs.
• AI and DSP blocks: 1,096 to 21,048 second-generation AI Tensor DSP blocks provide up to 1,211 TOPS INT8, supporting INT8/9/16/32, BFLOAT16, FP16/32, TF32, and complex arithmetic across fixed-point, floating-point, tensor, and vector modes.
• High-speed connectivity: Up to 32 GT SerDes at 256 Gbps and 176 GX SerDes at 128 Gbps using NRZ and PAM4 signaling; PCIe 7.0 x8 and PCIe 6.0 x16 with IDE support; up to 4x 1.6TbE or 10x 800GbE with hardened MAC, PCS, FEC, and MACsec; UCIe chiplet interface for modular expansion.
• Memory and security: External memory support spans DDR5, LPDDR4, LPDDR5/5X, and LPDDR6 with up to 9.84 Tbps bandwidth and inline memory encryption; Secure Device Manager provides hardware root of trust, post-quantum cryptography per CNSA 2.0, and FIPS 140-3 Level 2 certifiable options.

Why it matters

The Agilex 27 family's Armv9.2 processor subsystem and claimed mainline-ready design tools will influence Linux BSP and RTOS porting efforts for high-end embedded and aerospace applications, though actual upstream kernel support remains to be demonstrated. For open hardware and RISC-V ecosystems, the competitive pressure from a major FPGA vendor integrating modern Arm cores with 256 Gbps SerDes and PCIe 7.0 may accelerate similar capability pushes in open ISA-based alternatives. The QuartusIQ AI assistant and MCP connectivity in Quartus Prime Pro 26.3 also signals growing embedding of generative AI into proprietary EDA workflows, with implications for open-source FPGA tooling projects like Yosys and nextpnr.