AMD publishes ROCm Programming and Optimization Guides as structured handbooks

AMD has introduced the ROCm Handbooks, a new documentation format that reorganizes the platform's component-scattered documentation into structured, book-style volumes optimized for in-depth study and offline access. The series currently comprises two volumes: the AMD ROCm Programming Guide, which teaches HIP fundamentals from first kernel to platform installation, and the AMD ROCm Optimization Guide, which provides profiler-guided optimization patterns for experienced developers targeting AMD GPU architectures from Radeon workstations to Instinct data center accelerators.

The handbooks release in lockstep with ROCm versions, ensuring content-software parity, and are available in both PDF and HTML formats. The Programming Guide covers HIP C++ extensions, runtime APIs, memory management models, and five applied tutorials including matrix multiplication and k-means clustering. The Optimization Guide advances through three fundamental algorithm patterns—reduction, histogram, and matrix multiplication—with each step instrumented by profiler counters, plus architecture-specific compiler builtins including MFMA instructions for CDNA architectures.

Handbook structure and technical content

• Documentation architecture: The handbooks aggregate material from multiple ROCm component docs, add original chapters, and arrange content along sequential learning paths rather than the portal's component-organized structure.
• Programming Guide coverage: Four parts span GPU programming fundamentals, HIP runtime APIs (streams, graphs, cooperative groups, four memory types), five applied tutorials, and ROCm installation including source builds.
• Optimization methodology: The Optimization Guide enforces a profile-first approach, with each optimization pattern listing specific profiler counters to measure incremental improvements on target hardware.
• Algorithm patterns: Three progressive patterns—reduction (LDS bank conflicts, wavefront reductions), histogram (global to LDS atomics, two-kernel merge), and matrix multiplication (seven steps through tiling, double buffering, vectorization, launch bounds tuning, architecture-dispatching templates).
• Compiler builtins: Cross-architecture coverage includes DPP shuffles, lane permutations, and votes; CDNA-specific MFMA builtins span MI100 through newer Instinct architectures for matrix fused multiply-add operations.

Why it matters

Structured, offline-capable documentation lowers the barrier for developers migrating CUDA codebases to HIP or entering AMD GPU development without institutional support. The version-locked release model ensures that enterprise and HPC deployments can rely on documentation matching their installed ROCm stack, reducing integration friction that has historically complicated AMD GPU adoption against NVIDIA's mature CUDA documentation ecosystem.