CERN's SoCMake produces first radiation-hardened RISC-V ASIC prototype

The System-on-Chip Radiation-Tolerant Ecosystem (SOCRATES) at CERN has advanced to silicon with TriglaV, a prototype ASIC built using the SoCMake modular RISC-V framework. The chip incorporates triple modular redundancy, hardened interconnects, and memory protection for reliable operation in the LHC's radiation environment. While initially targeting high-energy physics detector readout and control tasks, the fault-tolerant design techniques are also applicable to automotive and industrial safety-critical systems.

TriglaV test results and SoCMake architecture

• SoCMake is a modular build framework for generating RISC-V SoC designs, part of the broader SOCRATES ecosystem
• TriglaV is the first fully radiation-hardened prototype ASIC produced with SoCMake, designed for LHC detector front-end electronics
• Fault-tolerance techniques include triple modular redundancy (TMR), hardened interconnects, and memory protection
• Current applications focus on control tasks and local data processing such as chip calibration; physics data processing remains longer-term
• The platform builds on prior use of programmable SoCs for edge computing in other domains, now adapted to ASIC designs for radiation-harsh environments

Why it matters

The work demonstrates that modular, open RISC-V SoC construction flows can produce real radiation-hardened silicon for some of the most demanding environments on Earth. If SOCRATES/SoCMake matures, it could lower barriers for academic and industrial teams building fault-tolerant embedded controllers without proprietary lock-in.