GCC 17 merges AVX10V1AUX support for AMD-Intel AI Compute Extensions

AMD engineers have landed initial AVX10V1AUX support into the GCC 17 compiler codebase, marking the first toolchain integration of this auxiliary instruction set extension. AVX10V1AUX serves as a bridge between early AVX10-capable processors and the fuller AVX10.2 specification, enabling neural network inference acceleration on hardware that predates complete AVX10.2 silicon.

The extension originates from the AI Compute Extensions (ACE) initiative, a rare cross-vendor collaboration between AMD and Intel to establish common ISA ground for AI workloads. GCC 17 exposes these capabilities through the new -mavx10v1aux compiler flag, though the compiler does not yet map this support to specific processor generation targets. The patches were developed and submitted by AMD engineers over several weeks before merging into GCC Git.

What AVX10V1AUX brings to GCC 17

• VNNI quantization support: AVX10V1AUX adds native VNNI INT8 and VNNI INT16 instructions, enabling vector neural network instructions for reduced-precision inference on early AVX10 hardware without requiring full AVX10.2.
• Instruction borrowing: The extension incorporates selected instructions from later AVX10 revisions, allowing software compiled with -mavx10v1aux to access a subset of AVX10.2 capabilities on earlier silicon.
• Compiler flag exposure: GCC 17 surfaces AVX10V1AUX through the dedicated -mavx10v1aux switch, though processor-specific targeting (e.g., -march=zn5, -march=graniterapids) does not yet incorporate these extensions.
• Cross-vendor ISA alignment: The extension emerges from the ACE (AI Compute Extensions) joint effort between AMD and Intel, representing coordinated vendor investment in compatible AI acceleration primitives rather than divergent proprietary extensions.

Why it matters

For Linux distributions and developers building AI inference workloads, AVX10V1AUX in GCC 17 reduces the hardware fragmentation problem where early AVX10 CPUs would lack VNNI acceleration available only on AVX10.2 parts. This particularly benefits PyTorch, ONNX Runtime, and oneDNN builds targeting broad x86_64 deployment, as maintainers can compile a single binary path that extracts neural network performance from both current and near-future AMD and Intel server processors without separate code paths for each vendor's timeline.