Linux 7.4 fixes Cache Aware Scheduling regression on AMD Ryzen AI 9 HX 370 hybrid chips

A regression fix has been merged for Linux 7.4 that addresses Cache Aware Scheduling problems on AMD's Ryzen AI 9 HX 370 'Strix Point' laptop SoC and potentially other hybrid Zen 5/5C processors. The issue, first reported in August by a Gentoo user running LLVM Clang with full link-time optimization, caused compilation tasks to become pinned to the eight smaller Zen 5C efficiency cores instead of migrating to the four higher-performance Zen 5 cores. Because the Zen 5C cores run at only 3.3 GHz versus 5.1 GHz and share half the L3 cache (8 MB versus 16 MB), this pinning produced dramatic slowdowns compared to kernels without Cache Aware Scheduling.

The fix changes how the scheduler resolves conflicts between two placement strategies: asymmetric packing, which favors higher-priority performance cores, and Cache Aware Scheduling, which seeks to keep a process's tasks within one last-level cache domain. The patch makes asymmetric packing win when it would move a task to an idle higher-performance core, on the basis that the frequency and cache gains outweigh LLC co-location benefits. The change was merged via the scheduler fixes pull request and is marked for back-porting to the Linux 7.2 and 7.3 stable branches.

Scheduler logic and hybrid core handling

• Asymmetric packing priority: The patch elevates asym packing above LLC balancing for both regular and active load balancing paths, reversing the previous behavior where Cache Aware Scheduling could override core performance upgrades.
• Zen 5/5C topology awareness: The fix specifically accounts for systems where little cores have substantially lower frequency ceilings (3.3 GHz vs 5.1 GHz) and reduced L3 cache (8 MB vs 16 MB), making LLC pinning doubly harmful for throughput.
• Workload trigger: The regression manifested during LLVM Clang full-LTO linking, a cache-intensive workload where task placement across the 12-core hybrid layout critically determines build performance.
• Back-port scope: The fix is targeted for Linux 7.4 Git and stable back-ports to 7.2 and 7.3, with potential applicability to other Ryzen SoCs combining Zen 5 and Zen 5C cores in asymmetric configurations.

Why it matters

Linux distributions shipping kernel 7.2 or 7.3 with Cache Aware Scheduling enabled, particularly those targeting mobile and workstation laptops with AMD Strix Point hardware, will see restored compilation and build performance once the back-port arrives. For developers running Gentoo, Fedora, or other source-based or CI-heavy workflows on hybrid AMD silicon, this eliminates a significant throughput regression that had forced workarounds or kernel downgrades. The scheduler change also establishes clearer precedence rules for future hybrid x86 designs where cache topology and core performance asymmetry will continue to diverge.