SpacemiT V100 is first RISC-V server chip with 46 cores, DDR5, PCIe 5.0
SpacemiT claims the V100 is the first processor fully compliant with the RISC-V server specification, combining 6 XiangShan high-performance cores with 40 efficiency cores.
Summary
SpacemiT announced the V100, a 46-core server-class RISC-V processor manufactured on 12nm with 120W TDP. The chip uses a hybrid design with 6 XiangShan Kunminghu V2R2 cores and 40 SpacemiT X100 cores running at 2.2–2.4 GHz. It supports dual-socket configurations for 92 total cores, eight-channel DDR5-4800 memory, and 52 lanes of PCIe 5.0.
V100 core configuration and server features
- Hybrid core design: 6 XiangShan Kunminghu V2R2 performance cores + 40 SpacemiT X100 efficiency cores, totaling 46 cores per socket
- Platform specs: 12nm process, 120W TDP, 2.2–2.4 GHz clock speeds
- Memory and I/O: Eight-channel DDR5-4800, 52 lanes of PCIe 5.0
- Scalability: Dual-socket support for up to 92 cores per server
- Server compliance: Claims first full RISC-V server specification support, including UEFI, ACPI, and SMBIOS
Why it matters
The V100 represents a notable step in RISC-V's push into server infrastructure, though its 12nm process and performance positioning lag behind contemporary x86_64 and Arm server offerings. Actual performance benchmarks will be needed to assess its competitiveness.
Original reference: www.phoronix.com →