STMicroelectronics launches STM32H7P4/H7P5 Cortex-M7 MCUs with Hardware Signal Processor, optional Neural-ART NPU

STMicroelectronics has unveiled the STM32H7P4 and STM32H7P5, two 520 MHz Arm Cortex-M7 microcontrollers targeting digital power, motor control, industrial sensing, and edge AI workloads. Both parts feature a Hardware Signal Processor (HSP) that accelerates FFT, matrix/vector operations, filtering, and convolution with 32-bit floating-point precision, alongside CORDIC and FMAC mathematical coprocessors. The STM32H7P5 adds an 85 GOPS Neural-ART NPU running at up to 520 MHz for TinyML inference, which ST claims can run an arc-fault circuit interrupter model 40 times faster than pure software on the Cortex-M7 core.

The MCUs include up to 2MB dual-bank flash with ECC, 736KB SRAM split across multiple buses, and extensive peripheral connectivity including three CAN FD interfaces, USB OTG Full-Speed, and external memory support via Octo-SPI and FMC. ST provides software support through the STM32CubeH7P package with HAL2 drivers, middleware, and application examples, plus specialized SDKs for motor control and digital power. Two development boards are available: the NUCLEO-H7P5II Nucleo-144 and the STM32H7P5I-DK Discovery kit with display and sensor peripherals. Sampling is underway for OEM customers, with mass production scheduled for January 2027 and pricing starting at $4.43 for 1MB flash variants in volume.

HSP and Neural-ART architecture

• Hardware Signal Processor (HSP): Dedicated 32-bit floating-point accelerator for FFT/IFFT, matrix/vector operations, filtering, and convolution; ST claims 5x faster FFT execution than software on the Cortex-M7 core, reducing CPU load in motor control and power conversion applications.
• Neural-ART NPU (STM32H7P5 only): 85 GOPS accelerator at up to 520 MHz for edge AI inference; ST demonstrates 40x speedup on an AFCI model versus Cortex-M7 software implementation, targeting TinyML and industrial safety applications.
• Memory hierarchy: Up to 2MB dual-bank flash with ECC, 736KB total SRAM divided into 192KB ITCM, 128KB DTCM, 320KB AXI, and 96KB AHB regions, plus 4KB backup SRAM and 1KB OTP; external memory expansion via Octo-SPI (PSRAM, NOR, HyperRAM, HyperFlash) and FMC (SRAM, PSRAM, NOR, NAND, SDRAM).
• Industrial peripherals: Two high-resolution timers with 1.9 ns resolution and 24 PWM outputs, three advanced motor-control timers, four 12-bit ADCs at 5 MSPS with 44 channels, three CAN FD controllers, and dual USB Type-C Power Delivery controllers.
• Security features: Readout protection, proprietary code readout protection, active tamper detection, secure firmware upgrade support, HASH accelerator for MD5/SHA-1/SHA-2/HMAC, and NIST SP 800-90B compliant TRNG.

Why it matters

The STM32H7P family brings previously separate signal-processing and neural-network acceleration IP into a unified Cortex-M7 platform, giving embedded Linux and RTOS developers a single part number for real-time control combined with on-device inference. For the open-hardware community, the availability of sub-$5 MCUs with hardware FFT and optional NPU lowers the barrier to building open-source motor drives, digital power supplies, and sensor fusion devices that can run machine learning without cloud dependency. ST's continued investment in STM32Cube tooling, while proprietary, provides a standardized baseline that Zephyr RTOS and other open-source embedded projects can target for driver porting efforts.