Open Hardware & RISC-V

Qwenputer experimental AI model integrates 32-bit RISC-V CPU into LLM weights

Key Takeaway

An experimental project has successfully embedded a functional 32-bit RISC-V CPU directly into the weights of the Qwen 3.5 4B model, using the model's internal state as RAM.

Summary

Engineer Divyansh Agrawal has introduced Qwenputer, an experimental implementation that embeds a 32-bit RISC-V CPU directly into the weights of the Qwen 3.5 4B Large Language Model (LLM). Unlike standard LLM modifications that rely on training, this CPU is implemented via 11 transformer layers placed in front of the original model, with weights determined by a compiler rather than machine learning.

The system utilizes the Gated DeltaNet (GND) state of the Qwen model to function as both RAM and a persistent filesystem. This architecture allows the model to execute C and MicroPython code, perform exact arithmetic operations to bypass LLM calculation errors, and even run software like DOOM, albeit at low speeds. Due to the added layers, the model size has increased to approximately 19GB, requiring at least 24GB of VRAM for operation.

Technical architecture of Qwenputer

  • CPU Implementation: The 32-bit RISC-V CPU consists of 11 transformer layers where weights are computed by a compiler rather than learned through training, ensuring the CPU passes official riscv-tests and matches QEMU behavior.
  • Memory Management: The project repurposes the Gated DeltaNet (GND) state as functional RAM, allowing the model to handle instructions and data without external runtime calls or tools.
  • Filesystem Integration: A filesystem is implemented using the DeltaNet state, providing 1,024 slots capable of holding up to 512 files, which can be made persistent by saving the conversation state.
  • Computational Accuracy: By offloading arithmetic to the embedded RISC-V core, the model overcomes the inherent precision and calculation weaknesses typical of standard transformer-based LLMs.

Why it matters

This experiment demonstrates a novel way to combine deterministic hardware logic with probabilistic AI models, potentially leading to more reliable AI agents. For the RISC-V ecosystem, it showcases the architecture's versatility as a target for unconventional computing paradigms like weight-embedded processing.

Original reference: www.tomshardware.com →